More memory is being embedded into system-on-chip (“SOC”) devices in order to provide increasing functionality. Many SOC devices have more than 50% of their area devoted to embedded memories. Ensuring these memories are valid and operating correctly is of the upmost importance for producing SOC devices. In addition, as memory content increases, the memories become more susceptible to defects and variations in the chip parametric as technology feature sizes decrease.
Any reasonable SOC solution requires extensive memory diagnostic capability (i.e., the ability to produce maps of failing memory bits or “bit fail maps”) in order to understand memory failure modes. This becomes critical to debugging memory marginalities, improving memory designs, identifying manufacturing process weaknesses, and developing excellent product yields.
To further complicate matters, larger sizes of memory blocks are making high speed collection of high quality diagnostic data much more difficult. Built-in self-test (“BIST”) solutions need to identify failing locations within just a few high speed clock cycles by observing memory outputs that may be located across a region of hundreds of microns.
FIG. 1 illustrates a block diagram for a traditional miscompare logic for memory diagnostics. A traditional miscompare logic comprises bit comparators 8a-8c, an OR gate 16, a fail counter 18, a comparator 26, and an AND gate 20. The bit comparator 8a comprises an XOR gate 10a, a multiplexer 12a, and a flip-flop 14a; the bit comparator 8b comprises an XOR gate 10b, a multiplexer 12b, and a flip-flop 14b; and the bit comparator 8c comprises an XOR gate 10c, a multiplexer 12c, and a flip-flop 14c. The number of bit comparators 8a-8c depends on a data width of the data from a memory under test (“MUT”). As such, the number of bit comparators 8a-8c can be adjusted to fit the data width from the MUT. The fail counter 18 comprises an adder 19, a multiplexer 22, and multi-bit flip-flops 24 for storing the counter value. The fail counter 18 counts the number of miscompare flags outputted by the OR gate 16.
The test engine (e.g., a BIST or other memory test engine) inputs test patterns having control commands, address(es), and data to the MUT to run diagnostics on the MUT. The MUT performs operations according to the test patterns. The results of those operations are outputted as stored data. The XOR gates 10a-10c receive the stored data from the MUT and expected data from the test engine to determine if there are any mismatches between the stored data and the expected data of the test patterns.
In particular, the XOR gates 10a-10c compare the stored data[0]-[n] and the expected data[0]-[n] bit-by-bit. For instance, a stored data[0] at bit position 0 and expected data[0] at bit position 0 are compared to each other by the XOR gate 10a to determine if there is a mismatch (also referred to as a miscomparison) between the two values. The output of the XOR gate 10a is coupled to an input of the multiplexer 12a. An output of the multiplexer 12a is coupled to an input of the flip-flop 14a. The flip-flop 14a can store the miscomparison found by the XOR gate 10a. The output of the flip-flop 14a is coupled to the OR gate 16. The output of the flip-flop 14a is also coupled to another input of the multiplexer 12a. When a diagnostic pause is generated by the AND gate 20, the diagnostic pause selects the flip-flop 14a's current output to output from the multiplexer 12a to the flip-flop 14a. In this manner, the diagnostic pause can freeze the state of the flip-flops 14a-14c to its last inputted value.
Likewise, the bit comparators 8b and 8c also have an XOR gate, a multiplexer, and a flip-flop that are serially connected to compare stored data and expected data at a relative bit position. Those findings are further inputted to the OR gate 16 for accumulation. If any one of the bit comparators 10a-10c provide a logic high (i.e., a miscomparison is found for one or more of the bits), the OR gate 16 will generate a miscompare flag indication at its output. Generally, a low logic signal can indicate that the bit-by-bit comparison resulted in a match and a high logic signal can indicate a miscompare flag was generated based on one or more miscomparisons.
Miscompare flags are accumulated by the fail counter 18. The miscompare signal from the OR gate 16 is inputted to the multiplexer 22 for selection of one of the multiplexer 22's input. The integer adder 19 adds one to the output of the multi-bit flip-flops 24 which keeps a running tally of the number of miscompare flags that have been generated. That increased value is inputted to the multiplexer 22 which is outputted to the multi-bit flip-flops 24 to store this increased value. If the miscompare signal is low, then the multiplexer 22 selects an input of the multiplexer 22 that is tied to the output of the multi-bit flip-flops 24 to maintain the value stored in the multi-bit flip-flops 24 at the currently stored value. If the miscompare signal is high, then the multiplexer 22 selects an input of the multiplexer 22 that is tied to the output of the adder 19 to increase the value stored by the multi-bit flip-flops 24 by one.
The outputted value of the multi-bit flip-flops 24 is inputted to the comparator 26 to determine if the fail counter value has reached a predefined threshold value of miscompare flags. If so, the comparator 26 issues a high logic value to the AND gate 20. Upon the next miscompare flag (i.e., when the miscompare signal goes high), the AND gate 20 will generate a diagnostic pause, which is inputted to the multiplexers 12a-12c to freeze the states of the flip-flops 14a-14c. 
Operationally, the miscompare logic generates a composite miscompare signal from the bitwise XOR results of the XOR gates 10a-10c. The AND gate 20 gates the composite miscompare signal with whether the value of the fail counter has reached the predefined threshold value to determine if the miscompare logic should pause. This architecture is limited in its maximum operating frequency by the fan-in from the XOR flip-flops, through the OR and AND gates, and the fan-out back to the flop-flops, all of which must be accomplished in one clock cycle. Thus, such miscompare logic system may be inaccurate due to not being able to perform the fan-in and fan-out within a cycle.
Therefore, it is desirable to provide methods, apparatuses, and systems for an extensible memory diagnostic solution. In such methods, apparatuses, and systems, it is also desirable to have one or more of the following key features: supporting high speed data collection with minimal circuit overhead; supporting large memories of varying dimensions with critical test outputs spaced along one or more edges; and providing key information in an easy to process state to simplify the software support required to generate memory bit fail maps.